PCB Tools
The agent has 16 PCB tools for layout and manufacturing.
Read & Inspect
pcb_get_summary
Overview of footprints, tracks, vias, zones, nets, layers.
pcb_get_summary
pcb_inspect
Inspect specific PCB sections.
pcb_inspect section="footprints"
| Parameter | Type | Description |
|---|---|---|
section | string | "footprints", "tracks", "vias", "zones", "nets", "net_impedance", "layers", "stackup" |
filter | string | Filter by reference, net, or layer. Required for net_impedance (exact net name). |
section="nets" includes each routed net's computed average impedance (model-aware) and a stackup_has_dk flag. section="net_impedance" with filter="<net>" returns the per-track impedance breakdown for one net (model, Zā/Z_diff, insertion loss per segment).
pcb_refill_zones
Refill all copper zones on the PCB. Run this after adding vias, moving components, or modifying traces.
pcb_refill_zones
pcb_run_drc
Run Design Rule Check.
pcb_run_drc output="detailed"
| Parameter | Type | Description |
|---|---|---|
output | string | "summary", "detailed", "grouped" |
pcb_get_pads
Get pad positions for footprints.
pcb_get_pads reference="U1"
pcb_get_footprint
Detailed footprint info with pads and courtyard bounds.
pcb_get_footprint reference="U1"
pcb_get_nets
Net list with connections and routing status.
pcb_get_nets net="VCC"
| Parameter | Type | Description |
|---|---|---|
filter | string | Match net names (e.g. "DATA*") |
include_pads | boolean | Include connected pads per net (default true) |
unrouted_only | boolean | Only nets with unconnected pads |
include_impedance | boolean | Attach computed average impedance (model-aware) to each routed net, plus a top-level stackup_has_dk flag |
Create & Modify
pcb_place
Batch footprint placement with rotation and layer selection.
pcb_place reference="U1" position=[50, 50] rotation=0 layer="F.Cu"
| Parameter | Type | Description |
|---|---|---|
reference | string | Component reference |
position | array | [x, y] coordinates in mm |
rotation | number | Rotation in degrees |
layer | string | "F.Cu" or "B.Cu" |
pcb_add
Add tracks, vias, zones, keepouts, graphics, text.
pcb_add type="track" net="VCC" points=[[10, 10], [20, 10]] width=0.25 layer="F.Cu"
| Parameter | Type | Description |
|---|---|---|
type | string | "track", "via", "zone", "keepout", "graphic", "text" |
net | string | Net name (for electrical elements) |
points | array | Coordinates |
width | number | Track width in mm |
layer | string | Layer name |
pcb_update
Batch update positions, nets, widths, locked state.
pcb_update references=["R1", "R2"] locked=true
pcb_delete
Delete elements by reference or UUID.
pcb_delete references=["R1"]
pcb_set_outline
Set board shape.
pcb_set_outline type="rectangle" width=50 height=30
| Parameter | Type | Description |
|---|---|---|
type | string | "rectangle", "polygon", "rounded_rectangle" |
width | number | Board width in mm |
height | number | Board height in mm |
corner_radius | number | Corner radius for rounded rectangle |
pcb_sync_schematic
Update PCB from schematic changes.
pcb_sync_schematic
pcb_export
Export Gerber, drill, STEP, POS files.
pcb_export format="gerber" output="/path/to/output"
| Parameter | Type | Description |
|---|---|---|
format | string | "gerber", "drill", "step", "pos", "bom" |
output | string | Output directory or file path |
pcb_autoroute
Run Freerouting autorouter on unrouted connections.
pcb_autoroute nets=["VCC", "GND"]
| Parameter | Type | Description |
|---|---|---|
nets | array | Specific nets to route (optional, routes all if omitted) |
pcb_setup
Read/write PCB board settings.
pcb_setup net_classes=[{name: "Power", track_width: 0.5, clearance: 0.3}]
Covers the full Board Setup dialog. action="get" returns every section; action="set" applies only the sections you provide. Commonly used parameters:
| Parameter | Type | Description |
|---|---|---|
action | string | "get" reads current settings, "set" applies changes |
physical_stackup | object | Stackup layers and materials: impedance_controlled, per-layer thickness_nm, dielectric epsilon_r / loss_tangent |
signal_integrity | object | Impedance analysis parameters: reference_frequency_hz, dk_measurement_frequency_hz, conductor_resistivity_ohm_m, conductor_roughness_m |
design_rules | object | Board-level constraints (clearances, track widths, via sizes) |
net_classes | array | Net class definitions including diff-pair width/gap |
tuning_profiles | array | Impedance/delay tuning profiles: target impedance + per-layer track geometry |
custom_rules | object | Custom DRC rules text (.kicad_dru), e.g. impedance_target constraints |
Other settable sections: board_editor_layers, board_finish, solder_mask_paste, dimension_defaults, zone_defaults, predefined_sizes, teardrops, length_tuning_patterns, text_and_graphics, zone_hatch_offsets, component_classes, net_class_assignments, drc_severities, grid, title_block, text_variables, origins. Call action="get" to see the exact shape of each.
For the REPLACE-semantics array sections (net_classes, tuning_profiles, net_class_assignments), passing an explicit empty array [] clears all entries (for net_classes, reduces to just Default).
For controlled impedance, set the stackup's dielectric properties, optionally tune the analysis parameters, and add impedance_target rules:
pcb_setup physical_stackup={
impedance_controlled: true,
layers: [{type: "BSLT_DIELECTRIC", dielectric: [{epsilon_r: 4.5, loss_tangent: 0.02, thickness_nm: 200000}]}]
} signal_integrity={ reference_frequency_hz: 2.5e9, conductor_roughness_m: 5e-7 }
Note that custom_rules and tuning_profiles set replaces the whole set ā for custom rules, get the current text, append, then set.