Auto Constraint
Auto Constraint uses AI to analyze your design and automatically generate net classes with appropriate trace widths, clearances, and routing rules.
Instead of manually calculating and entering constraints, the system examines your schematic's net names, components, and datasheet specifications to create optimized design rules.
How to Use
From the Agent Sidebar
Ask the agent to analyze your design:
Analyze my design and create net classes for all the nets
Or target specific areas:
Create net classes for the power section with appropriate trace widths for the 3.3V and 5V rails
From the Setup Dialog
- Open Board Setup
- Navigate to Net Classes
- Click the Auto-generate button
What It Generates
Auto Constraint creates net classes with calculated values for:
| Parameter | Based On |
|---|---|
| Trace width | Current carrying requirements, copper weight, temperature rise |
| Clearance | Voltage differential, board material, manufacturing capabilities |
| Via size | Current, thermal requirements, drill capability |
| Differential pairs | Gap and width for controlled impedance |
Example Output
A typical design might generate:
| Net Class | Trace Width | Clearance | Typical Nets |
|---|---|---|---|
| Power | 0.5mm | 0.3mm | VCC, 3V3, 5V, VBUS |
| Signal | 0.2mm | 0.2mm | GPIO, SPI_MOSI, I2C_SDA |
| High Speed | 0.15mm | 0.25mm | USB_D+, USB_D-, ETH_TX |
| Ground | 0.5mm | 0.2mm | GND, AGND, DGND |
How It Works
1. Net Name Analysis
The system identifies net types from naming conventions:
- Power rails — VCC, VDD, 3V3, 5V, 12V, VBUS
- Ground nets — GND, AGND, DGND, PGND
- High-speed signals — USB_D+, USB_D-, ETH_TX, HDMI_*
- Differential pairs — Signals with +/- or P/N suffixes
- Sensitive signals — VREF, AVCC, analog inputs
2. Component Examination
Connected components are analyzed:
- Regulators — Determines voltage rails and current capacity
- Connectors — Identifies external interfaces and requirements
- ICs — Reads power pin requirements from datasheet data
- Passives — Considers current ratings of inductors and capacitors
3. Constraint Calculation
Based on the analysis, values are calculated:
- Trace width = f(current, copper_weight, temp_rise, length)
- Clearance = f(voltage_diff, material, environment)
- Via size = f(current, thermal, drill_capability)
4. Application
The generated net classes are applied to your design. During PCB layout, DRC will enforce these rules automatically.
Tips for Best Results
- Name nets clearly — Use descriptive names like
VCC_3V3rather thanNET1 - Configure stackup first — Set your board stackup before generating classes for accurate impedance calculations
- Review power nets — Double-check current requirements for power traces
- Check high-speed signals — Verify impedance targets match your connector requirements
Manufacturing Constraints
Auto Constraint respects your manufacturing capabilities:
- Minimum trace width
- Minimum clearance
- Minimum via drill size
- Minimum annular ring
Configure these in Board Setup before running Auto Constraint.